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A Sub-5 nm MoS2 Transistor Hits 88 mV/dec, 'Beyond the Silicon Limit'. The Floor Is Still 60.

October 20, 2026 8 min read

On September 21, 2026, Nature Communications published a paper with an ambitious title: "Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit." The team, from Carnegie Mellon, the University of Florida, MIT, Texas A&M, the University of Southern California and Universidad Politécnica de Madrid, built transistors on a single layer of molybdenum disulfide (MoS2), a semiconductor about 0.7 nm thick, with a physical channel shorter than 5 nanometers. Their subthreshold swing is 88 mV per decade.

Carnegie Mellon's write-up, carried by Tech Xplore on October 6, quotes corresponding author Xu Zhang: "This new material can experimentally break silicon's limit. This is the first time that's ever been done."

Here is what stopped me. 88 is more than 60, and 60 mV per decade is the textbook floor for every conventional transistor at room temperature, silicon or not. So what exactly was beaten?

I am not a device physicist. I build software, as CTO of a LegalTech built on Claude and as an indie developer, and much of my job is deciding which "faster, better, first" claims to build on. So I read what the journal had online. When I opened the article page on October 20, it showed only the abstract on screen, but its Download PDF button gave the 10-page "Article in Press," the accepted manuscript that the journal says its final edited version will replace. The page also links a 16-page supplementary information file and the transparent peer review file. Everything below comes from those documents.

What a subthreshold swing measures

A transistor is a switch. A voltage on the gate lets current flow from the source to the drain through the channel. Below the threshold voltage, the current rises exponentially with gate voltage. The subthreshold swing is how many millivolts of gate voltage it takes to change that current tenfold. Lower is sharper, and a sharper switch shuts off with less voltage, which means less leakage and less power.

There is a floor. In a conventional transistor, electrons must climb over an energy barrier, and their thermal energy spreads them out. The best possible swing is ln(10) × kT/q, about 60 mV per decade at 300 K. That floor comes from temperature, not from silicon. MoS2 obeys it too.

For scale: if the swing stayed constant, which it does not, changing the current a millionfold (six decades) would take 6 × 88 = 528 mV of gate voltage at 88 mV/dec, against 360 mV at the floor.

What "beyond the silicon limit" means here

The comparison is at equal size. As silicon transistors shrink to a few nanometers, the gate loses its grip on the channel and electrons leak through even when the switch is supposed to be off. The abstract claims the MoS2 devices beat "the theoretical subthreshold limit of silicon" and the best emerging semiconductors "at comparable dimensions."

The supplementary figures show why the material helps. Their sketch of a state-of-the-art silicon gate-all-around transistor has a channel of about 15 nm and a body about 5 nm thick, while the MoS2 channel is about 0.7 nm thick, so the gate field reaches all of it. Silicon and germanium lose carrier mobility as they are thinned; 2D semiconductors keep theirs. The design adds two tricks: an air-gap spacer that cuts the parasitic capacitance between the source and drain and the channel, and a gate that overlaps the contacts, so it can also move the local Fermi level inside the MoS2 contact regions, where in silicon the contacts' Fermi level is "essentially fixed."

Their own simulations put a size on both tricks: with a high-κ material in place of the air gap (κ = 25), the swing would exceed 300 mV/dec, and with no gate-contact overlap it would rise to nearly 120 mV/dec. Those are model results, not measurements.

The process matters as much. The MoS2 is grown as a wafer-scale film by metal-organic chemical vapor deposition on sapphire, then transferred onto a 4-inch (10 cm) silicon wafer whose contacts are patterned by photolithography. The sub-5 nm gap between source and drain is not drawn by lithography: it is set by a sacrificial spacer about 4 nm thick, deposited by atomic layer deposition. To clear the excess metal, the main process peels it off with tape, which the authors note "is not CMOS compatible"; they also developed a wet-etch alternative with "no electron-beam lithography or tape-assisted steps." I could not tell from the text which of the two made the devices behind the 88 mV/dec.

The abstract does not give the silicon number it beats. The main text does. The team's quantum transport model, applied to a silicon double-gate transistor with a 3 nm body, gives a lower bound of about 150 mV/dec at a 5 nm channel and about 100 mV/dec at 8 nm, "which can be regarded as the intrinsic electrostatic limit of silicon." The method comes from the authors' "prior work." So the silicon side of this record is a simulation, not a measured silicon device. And 88 mV/dec is a representative device: across 138 measured devices, the median swing is 92 mV/dec, with a standard deviation of about 10. Both sit well under the modeled 150.

The axis decides the record. In 2016, a Science paper highlighted by Lawrence Berkeley National Laboratory's Molecular Foundry gated MoS2 with a carbon nanotube about 1 nm wide and reported a swing of about 65 mV/decade. A different Nature Communications paper, published July 11, 2026, notes that such ultra-short gates came with channel lengths exceeding 500 nm. In 2023, a Nature paper on indium selenide transistors scaled to a 10 nm channel reported a swing of 75 mV per decade. That paper also opened by saying no 2D transistor had yet surpassed state-of-the-art silicon, then claimed to, on transconductance and ballistic ratio. Both "firsts" can hold, because they sit on different axes. Even the roadmap's 12 nm is quoted on two axes: this abstract cites the IRDS industry roadmap's 12 nm plateau by 2037 as a channel length, while the 2023 paper cites its 12 nm as the point where gate-length scaling stops.

The peer review file is the better read

For this paper, Nature Communications publishes the reviewers' reports and the authors' replies. The file says the manuscript was first reviewed at another journal, and it holds two reviewers' reports from the Nature Communications round.

Reviewer 3 judged it "not suitable for publication in Nature Communications," on two grounds: a strongly negative threshold voltage, and a mobility never measured in the actual grown and processed MoS2. On that mobility, in the reviewer's reading, rested a claimed 85% "ballisticity"; with a more realistic one, it would be "close to 55-60%." Reviewer 4 recommended acceptance, with two queries. The first: the on/off ratio of 10⁸ "appears to be an overestimation," because the off current seemed to have been taken as the minimum measured value, not at a defined bias.

What changed before acceptance:

  1. The on/off ratio is now 1.1 × 10⁶, measured between gate voltages of -1 V and +1 V with 0.5 V on the drain. The old figure survives only as the "maximum current modulation" over the whole sweep, given in the main text as about 8 × 10⁷, and the on/off benchmarking panel was removed from Figure 4. Two definitions of the same ratio, a gap of about 70 times.
  2. The ballisticity analysis was removed entirely: the value, the model, the methods and the figures. The authors disagreed with the reviewer's reasoning and removed it anyway.
  3. The negative threshold voltage is now stated plainly: the devices run in depletion mode, which, the authors write, "would need to be addressed before the present devices could be implemented in industry-level integrated circuits."
  4. The gate dielectric is specified: about 5.5 nm of aluminum oxide, from three aluminum layers (nominally 1.5, 1.5 and 1.0 nm), each left to oxidize under ambient conditions overnight.

The headline numbers, under 5 nm and 88 mV/dec, were not what this round disputed. Reviewer 4 wrote that the revised work "presents a more complete and robust case."

What the paper does not show

Yield. The paper says the tape step clears the metal across the 4-inch wafer "with high yield" and that its 138 measured devices show "excellent reproducibility," but in what I could read, no document gives the share of working devices on the wafer. The 138 devices come with a swing histogram in the main text and, in the supplementary file, histograms of on-state conductance, maximum current modulation and off-state leakage. 138 measured devices is a sample, not a yield.

Uniformity and reliability. I found no wafer map. The 4.8 nm channel length is the mean of 980 measurements along a single device (standard deviation 0.9 nm, shortest below 3 nm), and the authors say that spread reflects variation inside one device "rather than device-to-device variation." Across devices, on-state conductance ranges from about 100 µS/µm to 1 mS/µm, a factor of ten. In the supplementary file, the temperature test is one representative device at 22 °C and 105 °C. In their reply, the authors list "device uniformity, reliability, and threshold voltage engineering" among the challenges that bringing 2D semiconductors to industrial chips still requires, and that no single study can solve at once.

A chip's voltage budget. The representative device in the supplementary file has a threshold of -1.1 V: it is partly on at zero gate voltage. The 1.1 × 10⁶ ratio spans a 2 V gate window, while the 2023 indium selenide paper cites the roadmap's ultimate silicon supply voltage as no less than 0.6 V.

Circuits. The paper describes none. Carnegie Mellon's write-up says the device "isn't ready for commercialization yet."

What I take from it as someone who ships software

  1. A "beats X" claim has an axis. Beats what, at which size, against a measured or a theoretical number? Here: a simulated silicon limit at the same channel length. By analogy, a model "beating" another on one benchmark, or a database fastest on one workload, says nothing yet about yours.
  2. Fix the window before quoting the number. The ratio was 10⁸ or 1.1 × 10⁶ depending on how "off" was defined. A p99 latency without its load, or an accuracy without its test set, is the software version.
  3. Read the review, not just the release. A peer review file is the changelog of a claim. I fact-check my own posts with Jev as a judge for the same reason: the useful output is the list of claims that did not survive.
  4. Scope the claim to the measurement. "It would be unreasonable to require a single study to resolve all of these challenges simultaneously," the authors replied. Fair, as long as the headline carries the scope too.

88 mV/dec under 5 nm is a real result, and "beyond the silicon limit" is true on its axis, against a modeled silicon. The floor is still 60, and the yield is still unknown.

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